`timescale 1ns/1ps

module tb;

	logic clk;
	logic rstn;
	
	always #5 clk = ~clk;
	
	initial begin
		clk <= 1'b1;
		rstn <= 1'b0;
		#30;
		rstn <= 1'b1;	
	end
	
	//rom 初始值
	initial begin
		$readmemh("inst_data_ADD.txt", tb.u_LilyRiscv_top.u_rom.rom_mem);
	end


	integer ii;
	initial begin
 		forever begin
			@(posedge clk) 
			$display("x27 register value is %d", tb.u_LilyRiscv_top.u_LilyRiscv.u_regs.GPR[27]);
			$display("x28 register value is %d", tb.u_LilyRiscv_top.u_LilyRiscv.u_regs.GPR[28]);
			$display("x29 register value is %d", tb.u_LilyRiscv_top.u_LilyRiscv.u_regs.GPR[29]);
			$display("---------------------------");
			// $display("---------------------------");
			// #100;
			// for(ii = 0; ii < 32; ii++) begin
			// 	$display("x%2d register value is %d", ii, tb.u_LilyRiscv_top.u_LilyRiscv.u_regs.GPR[ii]);
			// end
		end
	end
	
	LilyRiscv_top u_LilyRiscv_top(
		.clk   		(clk),
		.rstn 		(rstn)
	);

endmodule : tb